This invention relates to a level shifting circuit.
A conventional level shifting circuit is shown in FIG. 1. In FIG. 1, reference numeral 1 designates the input terminal of the circuit. An input signal which is to be subjected to level shifting is applied to the input terminal 1, which is connected to the base of a first transistor Q.sub.1. The emitter of the transistor Q.sub.1 is connected through a first resistor R.sub.1 to the collector of a second transistor Q.sub.2. The base of the transistor Q.sub.2 is connected to a base potential power supply source V.sub.B provided only for this transistor or for this transistor and other transistors. The emitter of the second transistor Q.sub.2 is grounded through a second resistor R.sub.2.
The level shifting circuit is organized as described above. Therefore, the transistor Q.sub.2 allows a predetermined current to flow in the ground potential direction, and the signal output which has been subjected to level shifting is directly provided at the collector of the transistor Q.sub.2, or obtained at the output terminal 2 through a suitable buffer (not shown).
The operation of this level shifting circuit will be described with reference to the following expressions under the conditions that, for convenience in description, in each of the transistors Q.sub.1, Q.sub.2, the current amplification is sufficiently large and the base-emitter forward voltage V.sub.be is constant irrespective of the current value.
The current I in the transistor Q.sub.2 is a constant current defined by the following expression: EQU I=(V.sub.B -V.sub.be)/R.sub.2
This current I also flows in the transistor Q.sub.1 and the resistor R.sub.1. Accordingly, when an input voltage E.sub.i is provided, the output voltage E.sub.O is: ##EQU1## In the above-described equation, ##EQU2## and all the terms in the brackets { }are constants. Therefore, irrespective of the input voltage E.sub.i, the output voltage E.sub.O is always lower by the constant value V.sub.s than the input voltage E.sub.i ; that is, the input voltage E.sub.i is level-shifted by V.sub.s to form the output voltage E.sub.O.
With respect to alternating current, when the transistor Q.sub.2 side is viewed from the output terminal 2, the impedance r thereof is much larger than the resistance R.sub.1. Therefore, ##EQU3## Thus, the loss between input and output may be neglected.
As is apparent from the above description, in the conventional level shifting circuit, the shift amount is constant. Therefore, this circuit is disadvantageous in the following points: In a case, for example, where the input signal is an AC signal with a DC potential variation, and the AC component is amplified by a differential amplifier, one side of which is fixed in potential, the dynamic range of the differential amplifier is limited by the DC variation. Accordingly, sometimes one is forced to employ a capacitive coupling circuit, or to decrease the gain of the differential amplifier. This is a serious problem in providing a level shifting circuit in the form of an integrated circuit (IC).
In general, in a silicon monolithic IC, the parameter f.sub.T of a PNP transistor is of the order of 1 to 2 MHz, except for that of a substrate type PNP transistor. Accordingly, it is impossible to apply such PNP transistors to an integrated circuit which can amplify a signal having a frequency band up to several megahertz substantially linearly by 20 to 25 dB. On the other hand, in an integrated circuit (IC), frequently the internal circuit must employ a direct coupling arrangement because of the required number of pins of the package, etc. Because of this fact, and the above-described fact that PNP transistors are not employable, the circuit transistor biasing condition is more shifted towards the supply voltage in the rear stage than in the front stage. On the other hand, the signal level becomes larger towards the rear stage; i.e., its amplitude becomes larger towards the rear stage, while the DC potential is shifted in such a manner that the difference between the DC potential and the supply voltage decreases. As a result, the dynamic range is gradually decreased towards the rear stage. This is undoubtedly undesirable.
In order to overcome the above-described difficulty, a constant voltage-type level shifting circuit comprising NPN transistors as shown in FIG. 1 is connected between stages, thus releasing the direct current condition. However, with the above-described conventional circuit, in the case where a DC component is superposed on the signal to be handled, the same DC variation appears even after the signal has been level-shifted. This is considerably disadvantageous in the case when the circuit is connected to a differential amplifier having one input connected to the aforementioned output and the other input receiving a fixed DC potential, as mentioned above. In the case of an integrated circuit, it is impossible to set the current at a large value because the power consumption of the chip is limited. That is, in the differential amplifier, the operating current and resistance applied to the emitter cannot be large, as a result of which the dynamic range in its operation as a differential amplifier is limited. Accordingly, the amplification of a high frequency signal with a DC variation may cause difficulties such that the differential amplifier, being saturated with the DC variation only, cannot amplify the required AC component.